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[ 01 ]Ventures

Synthesys

Synthesys is building semiconductor manufacturing for frontier compute: wafer fabrication, advanced packaging, test and assembly, and design enablement on one line, with every lot traced from first oxide to final test. Pre-production, and talking with early design partners at synthesys.one.

Synthesys
  • Fabrication, packaging, test and assembly on one line, with no external handoffs
  • Every lot traced: recipe, tool history and inline metrology from first oxide to final test
  • Wafer maps, defect Pareto and parametric data, not a single yield percentage

Bring a design. Leave with silicon. Synthesys is building semiconductor manufacturing for frontier compute: wafer fabrication, advanced packaging, test and assembly, and design enablement on one line, with every lot traced from first oxide to final test.

Synthesys is pre-production. The first line is in development, the 300 mm line is planned, and we are talking with early design partners. Nothing below describes a running fab.

The Problem: Silicon You Cannot See Into

Frontier compute is designed by more teams than ever and manufactured by very few. Getting a design to working silicon usually means a chain of separate vendors, and the customer sees little of what happens along it.

  • Fabrication, packaging and test sit with different suppliers, with a handoff and a queue at each step
  • A yield arrives as a single percentage rather than the data behind it
  • When a lot goes wrong, finding the tool, chamber and step responsible is slow, if it happens at all
  • Smaller teams struggle to get dedicated capacity at all

The Solution: One Line, Every Wafer Traced

Synthesys puts the whole flow under one roof so wafers move from fabrication through packaging and test without an external handoff, and it treats traceability as the product rather than an audit afterthought.

How It Is Designed to Work

Lot traceability. Every lot carries its recipe, tool history and inline metrology from first oxide to final test.

Yield you can see, not a number you are told. Customers get wafer maps, defect Pareto charts and parametric data, and known-good dies are proven before they are packaged.

Excursion handling. Affected lots are held, with a report naming the tool, chamber and step involved.

IP and data separation. Customers keep ownership of their design data, masks and dies, held apart from every other customer's.

Process capability. EUV patterning, and 2.5D and 3D integration for advanced packaging.

Who It Is For

AI accelerators, inference silicon, high-bandwidth memory, co-packaged optics and custom compute ASICs.

Capacity

  1. Shuttle. Shared multi-project wafer runs for proving a design, on mature processes.
  2. Pilot. Dedicated lots that take first silicon through production qualification, with full packaging and test.
  3. Volume. A reserved bay and tool time, priority dispatch and a shared yield programme.

Capacity and pricing are agreed per engagement.

What Happens Next

The work now is the first line and the first design partners. Synthesys is taking enquiries at synthesys.one.